ONFI Compatible

Designed to the ONFI 2.1 interface standard, our high-speed NAND interface is a forward-looking solution with backward compatibility.It’s an ideal road map for the future—a solution that meets existing demands, with the speed and scalability to enable better performance for almost every storage application.

View the specifications on ONFI.org

Will High-Speed NAND require new types of controllers?

To take full advantage of the capabilities of our High-Speed interface, controllers need to support the latest ONFI industry standard.

How is High-Speed NAND different from traditional NAND?

High-Speed NAND can read data at speeds up to 200 megabytes per second (MB/s) and can write data at speeds up to 100 MB/s.These speeds are achieved by leveraging the new ONFI 2.0 interface specification and a four-plane architecture with higher clock speeds.In comparison, conventional SLC NAND is limited to 40 MB/s for reading data and less than 20 MB/s for writing data.To maximize the performance benefits of High-Speed NAND, users must use the new ONFI 2.0 synchronous interface standard.

Is High-Speed NAND a proprietary or patented technology?

High-Speed NAND leverages the ONFI 2.0 standard synchronous interface to achieve its breakthrough performance.Host controllers can design-in High-Speed NAND with confidence knowing that ONFI 2.0 is an industry-standard interface that will be supported by other NAND architectures and devices.In addition, because ONFI 2.0 is backward-compatible with ONFI 1.0, designing in ONFI 2.0 is always a safe choice.

What NAND parts have been validated with the OMAP35x?

Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors.As we work with the OMAP35x team, the list of validated memory devices expands frequently.For the most current information, contact your local Micron support.

When I issue a Read ID command (90h) to a two-die NAND device, I get a device ID back that states it is a one-die NAND device.

In a two-die NAND device, where a single die is on each CE#, the device ID that is returned is per CE# for one die.For example, an 8Gb two-die NAND device with two CE# pins would return a 4Gb device ID on each CE#.See the Read ID section of the NAND device data sheet for more details.

I’ve heard that NAND has too many errors to boot from.Is this true?

With ECC, NAND can achieve bit error rates (BER) that are comparable with NOR, which is commonly used as a booting device.Applications that use NAND typically copy the booting code to DRAM and execute from DRAM.For more information, read Tech Note 29-16, which is geared to a specific processor, but the concepts can be applied generally.TN-29-19 is a very useful technical note on the general concepts of NAND.

Should I be marking blocks bad due to READ errors?

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Where can I find additional technical information about Micron NAND devices that is not covered in the device data sheets?

Additional Micron NAND Flash technical information—including details on performance enhancing commands—can be found on the Technical Notes page for NAND.

Why doesn't the NAND Flash device respond correctly to commands issued to it?

Be sure you are issuing a reset command (FFh) to the NAND device after powering on the device.A reset command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.

Where can I find simulation models for NAND Flash devices?

Micron posts Verilog, HSPICE, and IBIS models for NAND devices.To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.

Why am I getting a bit/byte error reading back the information I programmed into the NAND device?

Check that you are using the appropriate amount of error correction code (ECC) for the NAND device.The ECC threshold can be found in the "Error Management" section of the NAND device data sheet.Also ensure that none of the bad blocks marked by the NAND manufacturer (Micron) are used.See the "Error Management" section of the NAND device data sheet for more details on how to search for manufacturer-marked bad blocks.

How do I achieve greater PROGRAM/READ throughput for the NAND device?

To get the maximum PROGRAM/READ throughput for Micron NAND Flash devices, use the PROGRAM and READ CACHE operations.See the NAND device data sheet and our NAND Technical Notes Page for details on how to use these commands.

Do you support small block devices?

Currently, Micron only offers large block devices.For more information, please refer to Technical Note, TN-29-07:Small Block vs. Large Block NAND Devices.

How is Nvb specified?

Nvb is specified as the minimum number of valid blocks at the end of the P/E cycle spec.

I am using the correct amount of error correction code (ECC) for the NAND device, but I’m still seeing bit/byte errors in data I read back from the NAND device.

Make sure that you are issuing a READ STATUS command to the NAND device after any type of PROGRAM or ERASE operation.Checking status after a PROGRAM or ERASE operation will report whether the PROGRAM or ERASE operation was successful.If the READ STATUS command reports a failure with a PROGRAM operation, that data should be programmed somewhere else and the block being programmed should be retired.If the READ STATUS command reports a failure with an ERASE operation, that block should also be retired.

How much ECC do I need to support your devices?

We define our ECC requirement per 512-byte section.MLC NAND devices have a higher ECC requirement than SLC NAND due to the increased number of bits per cell.ECC requirements differ for designs, so consult the device data sheet for the amount of ECC needed.

I am seeing a lot of READ DISTURB errors.Can you tell me if there is a problem with your part?

READ disturb occurs when the same data is read repeatedly.By its nature, NAND technology has a very low occurrence of read-disturb errors.But, to mitigate any errors received due to read disturb, we recommend that users refresh the data to reduce the amount of times the same data is read.