| 特点 |
优势 |
| 密度 |
64Mb to 512Mb (LPSDR)
128Mb to 8Gb (LPDDR)
1Gb to 8Gb (LPDDR2) |
Provides flexibility for a variety of application designs |
| 配置 |
x16, x32 (LPSDR/LPDDR)
x16, x32, x64 (LPDDR2) |
Enables the use of fewer components to support wide-bus architectures |
| Voltage |
1.8V (LPSDR/LPDDR)
1.2V (LPDDR2) |
Helps reduce power consumption—a key advantage over standard DRAM |
| 时钟频率 |
Up to 167 MHz (LPSDR)
Up to 200 MHz (LPDDR)
Up to 533 MHz (LPDDR2) |
Provides performance comparable to SDR and DDR SDRAM, with the added advantage of power savings |
| 能耗 |
Refer to data sheet |
Delivers low power dissipation in standby and active modes, plus special mobile features to reduce power consumption for a more efficient design |
| Special Features |
Temperature-compensated self refresh (TCSR) |
Adjusts refresh timing to minimize power consumption at lower, ambient temperatures |
| Partial-array self refresh (PASR) |
Eliminates unnecessary row activations; refreshes 1/1, 1/2, 1/4, 1/8, 1/16 array |
| Deep-power down (DPD) |
Provides a low power state when data retention is not required |
| Programmable drive strength (DS) |
Enables drive currents to be reduced in point-to-point applications; easily adjusts to full, half, quarter, or eighth, based on memory bus loading |
| 温度范围 |
0˚C to +70˚C
0˚C to +85˚C
-40˚C to +85˚C
-40˚C to +95˚C
-40˚C to +105˚C |
Enables high performance in extreme environments |
| 封装 |
VFBGA |
Reduces footprint by up to 40% relative to standard SDR and DDR SDRAM for a smaller, more compact design; supports JEDEC-standard VFBGA pinout |
| Known good die |
Supports bare die with edge bond pads for easy stacking in SIP and MCP solutions |
| POP |
Saves board space by allowing a Mobile LPDRAM to be stacked on top of a processor so that the two components require only one footprint on the board; contact factory for availability |