DDR3 SDRAM

DDR3 SDRAM

领先市场的技术

By pushing the envelope in key areas like power consumption, signaling speeds, and bandwidth, our DDR3 brings new levels of performance to desktop, notebook, and server computing systems.

Tech Burst美光 DDR3 – 业内领先性能和支持

DDR3 是针对 CPU 系统的新一代高性能解决方案，该产品向多个关键技术领域发起性能极限挑战，例如能耗、信号传输速度和带宽等，将台式机、笔记本和服务器计算系统的性能提高到一个全新的水平DDR3 支持从 1066 到 1600 MT/s 的数据传输速率，时钟频率分别为 533 到 800 MHz，从而将 DDR2 的传输速度有效提高了一倍。DDR3 采用 1.5V 标准供电电压，相较 DDR2，其功耗最多可减少 30%。

DDR3 也带来了新的功率效率水平 – 我们的标准 1.5V 供电电压相较 DDR2 最多减少了 30% 的功耗，而我们的 1.35V 部分相对于标准 1.5V 消耗减少了另外的 20%。

如果您准备升级到 DDR3，我们随时为您提供帮助。作为行业领军企业，我们的装备专业精良，能够帮助您整理技术细节，并针对您的应用情况向您推荐最佳的 DDR3 解决方案。

DDR3 SDRAM 料件目录和文档


Balancing Power and Performance for Tablet and Ultrathin-Client Computing
平板电脑和瘦客户机在不断改变计算的发展路线以及内存要求。这些功能强大、高度移动的个人计算设备，在内存性能需求和电池寿命限制之间把握好分寸，更不用说空间限制。Our new 1.35V DDR3Lm specifically targets the ultrathin-client market with an optimal combination of high performance (data rates up to 1600 MT/s), low power usage (with tight IDD6 specs, 50% self refresh power savings versus standard DDR3L, and TCSR enablement), cost efficiency, and footprint size (x32 options)—the best of LPDDRx and DDRx technologies, blended into one.

为高存储需求的系统提供支持
如果您的新硬件设计的目标主要是提高性能，那么我们是您的理想选择。我们的 DDR3 能够满足新一代系统的内存需求。其带宽有了显著增加，传输速度可达 1600 Mb/s。最佳状态时，数据传输速率相当于每秒传输一份约 100,000 页的文件。

特点 优势
Package FBGA Enables better electrical performance and speed
Pinout Improved pinout Improves signal integrity, power and ground distribution, and reliability
Voltage 1.35V, 1.5V Reduces memory system power demand
密度 1Gb, 2Gb, 4Gb Enables large memory subsystems
Internal Banks 8 Provides better back-to-back access and performance
Speed DDR3-1066, DDR3-1333, DDR3-1600 Provides migration path for higher bus speeds
Termination DRAM on-die termination (ODT) Improves write signaling
Data Strobes Differential or single-ended Improves system timing margin by reducing strobe crosstalk
Leveling Improved read/write leveling Allows better control of time delta, data capture, and receiver timing
System Synchronization Master reset Improves stability

类型 安全 标题和描述 编号 更新日期 文件大小
IBIS Behavioral Models: 美光多年前就已成为 IBIS 开放论坛的一员，完全支持 IBIS 规范。美光的网站上提供其大部分产品的 IBIS 模型以供下载。 TN-00-07 2009/11 163.98 KB
Thermal Applications: 定义了测量和确保美光零件和模块不超过允许的最高温度的一般方法和标准 TN-00-08 2010/05 252.18 KB
Understanding Quality and Reliability Requirements for Bare Die Applications: 介绍了 Bare Die 应用的质量和可靠性要求 TN-00-14 2009/10 152.83 KB
Recommended Soldering Parameters: 定义了美光科技公司产品的推荐连接技术和参数。 TN-00-15 2007/03 69.09 KB
Uprating of Semiconductors for High-Temperature Applications: 描述了与提升温度有关的问题，以及在制造环境规范之外使用零件和/或系统的相关风险 TN-00-18 2010/05 428.33 KB
Understanding Signal Integrity: 描述了从新产品构思直至产品寿命结束的整个过程中，如何发挥内存设计、测试和验证工具的最大优势 TN-00-20 2009/12 1.52 MB
SEMI Wafer Map Format: 美光采用了经国际半导体设备与材料联盟 (SEMI) 批准的晶圆图文件格式。使用 SEMI 的格式，美光的客户可以放心，因为他们将始终收到规格统一、兼容、可靠的晶圆图文件。 TN-00-21 2009/02 110 KB
Thinning Considerations for Wafer Products: 有关优化晶圆薄化工艺以满足特定客户需求的信息 TN-00-19 2009/10 73.58 KB
DDR3 Power: Estimates, effects of bandwidth, and comparisons to DDR2 2009/12 598.62 KB
DDR3 RDIMMs Channel: Basics, topology, simulations, and timing 2009/12 1.15 MB
Server Memory Solutions for the Impending Data Center Power Crisis: Facts about data center energy consumption and information about how to achieve significant power savings with Micron's low-voltage memory modules for servers. White Paper 2009/12 309.03 KB
DDR3 Thermals: Thermal limits, operating temperatures, tools, and system development 2009/12 1.32 MB
DDR3 - What's New: Technology trends, market forecast, road maps 2009/12 404.43 KB
PCN/EOL Systems: 介绍了美光产品的变更通知和寿命终结系统。 CSN-12 2012/04 79.21 KB
Wafer Packaging and Packaging Materials: 提供了有关装运美光产品时使用的各种材料的完整装运和回收信息。 CSN-20 2011/09 776.24 KB
Bare Die SiPs and MCMs: 描述了 Bare Die SiP 和 MCM 的设计考虑因素。 CSN-18 2009/04 151.06 KB
Shipping Quantities: 提供了料件数量表格。 CSN-04 2012/04 472.27 KB
Micron KGD Definitions: 描述了美光 KGD-C1 和 KGD-C2 DRAM 芯片的测试规格和参数 CSN-22 2009/07 65.52 KB
Micron Component and Module Packaging: 解释了美光的封装标签和程序。 CSN-16 2012/02 887.13 KB
ESD Precautions for Die/Wafer Handling and Assembly: 介绍了在工作场所中控制 ESD 的好处，包括提高产量和改善质量与可靠性，最终可以缩减制造成本。 CSN-24 2010/08 119.08 KB
Electronic Data Interchange: 描述了 EDI 传输的装置、协议和联系方式。 CSN-06 2005/09 53.5 KB
RMA Procedures for Packaged Product and Bare Die Devices: 概括介绍了标准的退货授权 (RMA) 程序，以及与 bare die RMA 的对比。 CSN-07 2010/10 82.64 KB
ISO System Management Standards: 描述了 ISO 系统管理标准。 CSN-08 2004/04 39.18 KB
The Future of Memory and Storage: 概述了主存和闪存的发展趋势 2009/12 1.54 MB
Main Memory Technology Direction: Technology trends, customer requirements, intro to DDR3 2009/12 531.53 KB
Calculating Memory System Power For DDR3 : Details how DDR3 SDRAM consumes power and provides the tools that system designers can use to estimate power consumption. TN-41-01 2007/05 1.12 MB
DDR3 ZQ Calibration: Describes how the DDR3 SDRAM driver design has been enhanced TN-41-02 2008/02 250.61 KB
DDR3 Dynamic On-Die Termination : With DDR3, dynamic ODT provides systems with increased flexibility to optimize termination values for different loading conditions TN-41-04 2008/03 370.26 KB
DDR3 Termination Data Strobe : Provides guidelines for using the TDQS feature to reduce signal integrity issues associated with mismatched DQS loading in in combined x4-based/x8-based systems TN-41-06 2008/03 152.41 KB
DDR3 Power-Up, Initialization, and Reset: Describes power-up, initialization, and reset with DDR3. TN-41-07 2008/10 504.77 KB
DDR3 SDRAM System-Power Calculator: Version 0.9 2010/12 195.3 KB
DRAM Component Part Numbering System: DDR3/DDR2/DDR/SDR SDRAM、Mobile LPDRAM 和 RLDRAM 零件的料件编号向导 2012/04 36.89 KB
FBGA Date Codes: FBGA 封装零件的日期代码 2005/08 22.36 KB
Moisture Absorption in Plastic Packages: Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 2010/02 87.26 KB
Accelerate Design Cycles with Simulation Models: 美光会提供必要的工具和指导，以在实际布局前对新设计进行检验。此技术要点讨论了软件模型支持、信号保真性优化和逻辑电路设计。 TN-00-09 2010/02 206.91 KB
Design Guide - Dealing with DDR2/DDR3 Clock Jitter: 探索了 DDR2/DDR3 的时钟抖动规范，并提供了规范应用及冲突处理方面的指导 TN-04-56 2008/09 272.53 KB
Micron Wire-Bonding Techniques: 此技术要点提供了丝焊技术的指导，可用于美光产品的镍钯 (NiPd) 和铝制接合焊盘。 TN-00-22 2010/11 66.13 KB
Micron BGA Manufacturer's User Guide: 提供相关信息，帮助顾客轻松将最前沿的和传统的美光球栅阵列 (BGA) 封装整合到制造流程中。此指南旨在提供一系列高水平指导，并附有参考手册，其中介绍了封装相关和制造工艺流程的典型做法。 CSN-33 2011/07 353.32 KB
DDR3L SDRAM System-Power Calculator:  2011/07 197.81 KB
Product Marks/Product and Packaging Labels: 介绍了产品料件的标记，以及产品和封装的标签。 CSN-11 2012/04 724.89 KB
DDR3 Advantages Presentation: Covers power, speed, performance, and more 2009/12 365.19 KB
Error Correction Code in SoC FPGA-Based Memory Systems: This presentation will examine the potential sources and implications of soft errors and explain an error detection and correction method implemented by Altera and Micron to make embedded systems more resilient to these types of soft errors. 2012/04 361.92 KB
Industrial and Multi-Market Applications Flyer: 我们拥有广泛而稳定的 IMM 式存储解决方案，有助于推动汽车、工业、医疗、制造业和其它多类细分市场的技术发展。 产品宣传页 2011/08 593.95 KB
Bypass Capacitor Selection for High-Speed Designs: 描述了高速设计的旁路电容选择。 TN-00-06 2011/03 481.9 KB

请注意：要查看安全文档 (安全锁)，请登录或单击某个安全文档以请求访问。

What is the output driver impedance for DDR3?
The default output driver impedance for DDR3 is 34 ohms.The impedance is based on calibration to the external 240 ohm resistor, RZQ.
What is the operating voltage?
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V.
What is the "MPR"?
MPR is a multi-purpose register.It is a specialized register designed to allow predefined data to be read out of the DRAM.Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16.Two locations in the MPR are defined.One allows the readout of predefined data burst—in this case, 01010101.The other location is used to output the refresh trip points from the on-die thermal sensor.
What is the RESET# pin used for?
RESET# is the master reset for the DRAM.It is an active LOW, asynchronous input.When the RESET# is asserted, the DRAM outputs and ODT will tri-state.The DRAM counters, registers, and data will be unknown.A RESET must be performed as part of the power-up and initialization sequence.During this sequence, the RESET# must remain LOW for a minimum of 200µs.After power-up and initialization, RESET# may be asserted at any time.Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
Will Micron support an extended temperature range for DDR3?
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.
What is "ZQ Calibration"?
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground.In DDR3, two different calibration commands exist:ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS).ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment.ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
What is "write leveling"?
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks.Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM.Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM.A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
How do I determine the amount of time between ZQCS commands?
Each ZQCS command can correct a minimum of 0.5 percent impedance error within 64 clocks.To calculate the ZQCS interval, use the following formula:ZQCS Interval =ZQCorrection (Tsens x Tdriftrate) + (VSens x Vdriftrate) For the sensitivities, use the MAX number from the ODT voltage and temperature sensitivity table in the component specification.Drift rates will vary from system to system.ZQCorrection equals 0.5%/64 clocks.
How do I determine my CAS WRITE latency (CWL)?
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
Can I run Micron’s DDR3 memory at clock speeds slower than 300 MHz?
Yes. Micron supports the optional feature to disable the DLL.This feature allows the DRAM to operate at frequencies slower than 125 MHz. A minimum clock rate is not specified, but the timing still must satisfy the refresh interval (tREFI).When operating in DLL disable mode, special conditions apply:- no support of on-die termination (ODT); ODT must be disabled or turned off - both CL and CWL must be equal to 6 - data out is no longer edge-aligned to the clock and read latency will be AL + CL - 1 tCK
What component densities are available?
JEDEC has defined DDR3 densities of 512Mb–8Gb; Micron plans to support 1Gb through 4Gb.
What is the difference between the ZQCL and ZQCS commands?
ZQCL stands for ZQ calibration long.This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete.After power-up and initialization, the command can be issued any time the DRAM is idle.These subsequent commands only require 246 clocks.This command is used when there is more impedance error correction required than a ZQCS can provide.ZQCS stands for ZQ calibration short.This command can be performed any time the DRAM is idle.One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
What is Dynamic ODT?
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command.When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst.Once the burst is complete, the termination will be changed back to the Rtt_Nom value.Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
What is burst chop?
Due to DDR3's use of the 8n-prefetch architecture, a true burst of 4 is not possible with most designs.Burst chop mode (BC4) is unique to DDR3.In this mode, the last 4 bits of the burst are essentially masked.Timing in BC4 cannot be treated like a true BL4.For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode.While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized.

DDR3 SDRAM

相关信息