DDR SDRAM

DDR SDRAM

DDR：仍是许多新设计的理想选择

我们刚刚推出 DDR SDRAM 时，它曾是革命性的前沿技术，实现了在时钟信号的上升沿和下降沿都可传输数据，并且相对 SDRAM 性能有了极大提升。因为 DDR 仍将是许多新设计的理想选择，所以我们致力于长期支持此产品。

motherboard blue加倍努力以满足主流内存需求

DDR 长期支持
我们知道许多客户在将来仍会继续在设计中使用 DDR 解决方案。我们致力于利用我们广受认可的技术、上乘的质量和行业领先的制造效率，在未来继续长期提供 DDR 产品。


DDR SDRAM 料件目录和文档


详细具体的技术帮助
我们致力于在内存业务领域提供独一无二的出色技术支持。从 FAE、技术要点和数据表，到模拟模型、计算器和开发工具，我们的目标是帮助您轻松整合具有业内最高品质的内存产品。

DDR SDRAM 工具箱
我们的 DDR SDRAM工具箱是一个技术资源集中存储库，可以为从事使用 DDR 的系统级产品开发的设计人员提供帮助。您可以在此处浏览并了解我们的 DDR 技术要点、DDR 系统功率计算器、美光/主板组合清单及其他标准和规范。

DDR SDRAM 工具箱

RoHS 5/6 和 6/6
符合 RoHS 6/6 标准的全套 DDR 元件组合，配之以一套适用于豁免应用行业的符合 5/6 标准的产品，为客户提供了多种选择。

更大的操作温度范围
操作温度范围更为宽泛，这使产品即使面临高压力的网络、通信、工业和汽车工作环境也可以保持卓越的性能。

规格 描述
密度 256Mb, 512Mb, 1Gb
配置 x4, x8, x16
供电电压 2.5, 2.6V
时钟频率 133–200 MHz
Data Rate DDR-266 to DDR-400B
温度范围 0°C to +70°C, 
–40°C to +85°C
–40°C to +105°C
封装 54-, 60-ball FBGA 
66-pin TSOP

类型 安全 标题和描述 编号 更新日期 文件大小
IBIS Behavioral Models: 美光多年前就已成为 IBIS 开放论坛的一员，完全支持 IBIS 规范。美光的网站上提供其大部分产品的 IBIS 模型以供下载。 TN-00-07 2009/11 163.98 KB
Thermal Applications: 定义了测量和确保美光零件和模块不超过允许的最高温度的一般方法和标准 TN-00-08 2010/05 252.18 KB
Understanding Quality and Reliability Requirements for Bare Die Applications: 介绍了 Bare Die 应用的质量和可靠性要求 TN-00-14 2009/10 152.83 KB
Recommended Soldering Parameters: 定义了美光科技公司产品的推荐连接技术和参数。 TN-00-15 2007/03 69.09 KB
Uprating of Semiconductors for High-Temperature Applications: 描述了与提升温度有关的问题，以及在制造环境规范之外使用零件和/或系统的相关风险 TN-00-18 2010/05 428.33 KB
Understanding Signal Integrity: 描述了从新产品构思直至产品寿命结束的整个过程中，如何发挥内存设计、测试和验证工具的最大优势 TN-00-20 2009/12 1.52 MB
SEMI Wafer Map Format: 美光采用了经国际半导体设备与材料联盟 (SEMI) 批准的晶圆图文件格式。使用 SEMI 的格式，美光的客户可以放心，因为他们将始终收到规格统一、兼容、可靠的晶圆图文件。 TN-00-21 2009/02 110 KB
Thinning Considerations for Wafer Products: 有关优化晶圆薄化工艺以满足特定客户需求的信息 TN-00-19 2009/10 73.58 KB
Decoupling Capacitor Calculation for a DDR Memory Channel: Provides a decoupling capacitor calculation for a DDR memory channel TN-46-02 2004/12 151.37 KB
Calculating DDR Memory System Power: Describes how to calculate DDR memory system power. TN-46-03 2005/03 336.91 KB
General DDR SDRAM Functionality: Describes DDR SDRAM functionality TN-46-05 2001/12 254.8 KB
Termination for Point-to-Point Systems: Provides a basic understanding of transmission line theory that is important to insure signal integrity in today's high-speed digital systems. TN-46-06 2011/03 356.29 KB
DDR333 Design Guide for Two-DIMM Unbuffered Systems: Describes DDR333 design guide for two-DIMM unbuffered systems TN-46-07 2002/12 5.93 MB
Designing for 1Gb DDR SDRAM: Provides system designers with essential information relevant to utilizing the 1Gb double data rate (DDR) synchronous dynamic random access memory (SDRAM). TN-46-09 2009/11 175.43 KB
DDR SDRAM Point-to-Point Simulation Process: Covers rarely addressed areas of the DDR SDRAM point-to-point simulation process TN-46-11 2005/07 330.05 KB
Mobile LPDDR Versus Standard DDR SDRAM: An overview of the functional and mechanical differences between low-power and standard DDR and a description of exclusive features of LPDDR TN-46-15 2007/12 432.44 KB
Mobile LPDRAM Unterminated Point-to-Point System Design:Layout and Routing Tips: Provides guidance for the development of multilayer board designs TN-46-19 2008/11 552.55 KB
PCN/EOL Systems: 介绍了美光产品的变更通知和寿命终结系统。 CSN-12 2012/04 79.21 KB
Wafer Packaging and Packaging Materials: 提供了有关装运美光产品时使用的各种材料的完整装运和回收信息。 CSN-20 2011/09 776.24 KB
Bare Die SiPs and MCMs: 描述了 Bare Die SiP 和 MCM 的设计考虑因素。 CSN-18 2009/04 151.06 KB
Shipping Quantities: 提供了料件数量表格。 CSN-04 2012/04 472.27 KB
Micron KGD Definitions: 描述了美光 KGD-C1 和 KGD-C2 DRAM 芯片的测试规格和参数 CSN-22 2009/07 65.52 KB
Micron Component and Module Packaging: 解释了美光的封装标签和程序。 CSN-16 2012/02 887.13 KB
ESD Precautions for Die/Wafer Handling and Assembly: 介绍了在工作场所中控制 ESD 的好处，包括提高产量和改善质量与可靠性，最终可以缩减制造成本。 CSN-24 2010/08 119.08 KB
Electronic Data Interchange: 描述了 EDI 传输的装置、协议和联系方式。 CSN-06 2005/09 53.5 KB
RMA Procedures for Packaged Product and Bare Die Devices: 概括介绍了标准的退货授权 (RMA) 程序，以及与 bare die RMA 的对比。 CSN-07 2010/10 82.64 KB
ISO System Management Standards: 描述了 ISO 系统管理标准。 CSN-08 2004/04 39.18 KB
Competitive DDR Memory Subsystems: DDR milestones and platform design 2009/12 2.64 MB
DDR System Design Considerations: DDR overview 2009/12 3.46 MB
The Future of Memory and Storage: 概述了主存和闪存的发展趋势 2009/12 1.54 MB
DDR SDRAM System-Power Calculator:  2010/01 55.81 KB
DRAM Component Part Numbering System: DDR3/DDR2/DDR/SDR SDRAM、Mobile LPDRAM 和 RLDRAM 零件的料件编号向导 2012/04 36.89 KB
FBGA Date Codes: FBGA 封装零件的日期代码 2005/08 22.36 KB
Moisture Absorption in Plastic Packages: Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 2010/02 87.26 KB
Accelerate Design Cycles with Simulation Models: 美光会提供必要的工具和指导，以在实际布局前对新设计进行检验。此技术要点讨论了软件模型支持、信号保真性优化和逻辑电路设计。 TN-00-09 2010/02 206.91 KB
Hardware Tips for Point-to-Point System Design: Provides hardware tips for point-to-point system design, termination, and layout TN-46-14 2008/06 376.6 KB
Initialization Sequence for DDR SDRAM: Describes the initialization sequence and configurable device parameters. TN-46-08 2010/08 294.95 KB
Micron Wire-Bonding Techniques: 此技术要点提供了丝焊技术的指导，可用于美光产品的镍钯 (NiPd) 和铝制接合焊盘。 TN-00-22 2010/11 66.13 KB
Micron BGA Manufacturer's User Guide: 提供相关信息，帮助顾客轻松将最前沿的和传统的美光球栅阵列 (BGA) 封装整合到制造流程中。此指南旨在提供一系列高水平指导，并附有参考手册，其中介绍了封装相关和制造工艺流程的典型做法。 CSN-33 2011/07 353.32 KB
Product Marks/Product and Packaging Labels: 介绍了产品料件的标记，以及产品和封装的标签。 CSN-11 2012/04 724.89 KB
Industrial and Multi-Market Applications Flyer: 我们拥有广泛而稳定的 IMM 式存储解决方案，有助于推动汽车、工业、医疗、制造业和其它多类细分市场的技术发展。 产品宣传页 2011/08 593.95 KB
Bypass Capacitor Selection for High-Speed Designs: 描述了高速设计的旁路电容选择。 TN-00-06 2011/03 481.9 KB

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On DDR, what happens when DQS write postamble (tWPST) maximum specification is exceeded?What problems could this cause?
The tWPST maximum specification is not a device limit.The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
On DDR, can the allowed jitter tolerance be larger than +/-150ps if we use a clock of 120 MHz instead of 133 MHz?Can the allowed jitter tolerance be larger if the device is faster?
The part may have more tolerance or margin to jitter than 150ps at 133 MHz, but Micron still has the same specification for all speeds.Micron does not relax jitter specifications for a lower speed.
Is VREF required during self refresh?I would like to put DDR memory in self refresh mode and turn off power to the CPU (the system is battery-operated).Can I disable VREF and still have correct self refresh operation?
Yes. VREF is required during self refresh.All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits.Again, VREF must not be disabled after the DDR memory is put into self refresh mode.Doing so could easily result in inadvertently exiting self refresh.You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD.DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver.Because the VREF pin is used primarily as an input to this circuit, its current draw is low.It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin.Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
On DRAM, can a READ or WRITE command be given instead of a refresh?
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed.(The different row addresses are the same number of rows as the number of REFRESH cycles.For example, in the case of 8,192/64ms, the number of rows equal 8,192.)With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
What is the maximum junction temperature at which DDR SDRAM functionality is guaranteed?
Please refer to page 3 of Micron’s technical note on thermal applications:TN-00-08.If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.
What is the difference between no connect (NC), no function (NF), and do not use (DNU) pins?How should external connections to them be handled?
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed.Micron recommends that no external connection be made to this pin.However, if a connection is inadvertently made, it will not affect device operation.Sometimes NC pins could be reserved for future use.Refer to the part’s data sheet to confirm whether the pin is reserved for future use.An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation.Micron strongly recommends that no external connection be made to this pin.A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed.Micron requires that no external connection be made to this pin.Refer to the part’s data sheet for more details.
On DRAM, can unused DQ (data) pins be left floating?
Micron recommends that unused data pins be tied HIGH or LOW.Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level.Unused pins can be connected to VDD or ground through resistors.
Can you provide a brief description of the necessary circuit functionality we would need to employ to transition from EDO to SDRAM technology?
Synchronous DRAM, as its name suggests, is a synchronous device and is a little different from EDO.SDRAM are directly tied to the same system clock that drives all of the other subsystems.SDRAM uses a dual-bank architecture—an interleave technique that essentially allows one cell to be read while another is being prepared for a cell access.This "cell hopping" eliminates downtime between cell activities and provides good performance improvement.Since the SDRAM will operate at higher speeds, attention needs to be paid to signal layout, including transmission line techniques such as series-terminating resistors.A consequence of signal layout could be noise due to faster clocks, crosstalk, etc.At the very least, an SDRAM controller is necessary for transitioning from EDO to SDRAM technology.
Can I get samples?
Yes. Talk to your service representative.
A customer uses a DDR -6T part at 333 MHz. Can he substitute a faster speed grade part (DDR400, -5B) without encountering problems due to the 2.6V operation?Can the customer run the part at -75 speeds?
Yes, all speed grades are backward-compatible.So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
Do I need a separate voltage regulator to supply Vref power?
How Vref is supplied depends on the system design.Many multi-drop systems (where there are several modules and a need for Vtt on the system board) already have a designated voltage regulator for DDR memory.In this case, the voltage regulator may have a dedicated tap for Vref.Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between Vdd and Vss.
How long does Micron plan to support DDR?
Micron has an extensive customer base across all four densities (256Mb–1Gb) of DDR and plans to support it for several years.Contact your local Micron sales representative for direction on the preferred part number to qualify.
How long does Micron plan to support 3.3V SDRAM?
Micron has an extensive customer base across all four densities (64–512Mb) of SDR and plans to support it for several years.Contact your local Micron sales representative for direction on the preferred part number to qualify.
Does Micron provide VHDL models for DDR parts?
No. Micron no longer supports VHDL models.We can, however, provide a generic 8 Meg x 8 model (MT46LC8M8) that can be scaled to the desired model dimensions.It’s a good starting point for building a compatible DDR model.To obtain this file, contact your Micron representative or a Micron applications engineer.You could also contact Denali or Synopsys to obtain one of their models.Or you could use a suitable multi-language simulator (like Modelsim) that cosimulates Verilog and VHDL and then download our Verilog model.

DDR SDRAM

相关信息

DDR 工具箱