VLP Mini DIMM

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VLP Mini-DIMM：优质网络模块

我们的高密度 VLP Mini-DIMM 极大地提升了电信通讯、网络以及计算刀片式服务器的总体存储能力并与 ATCA 标准兼容。


lan switch card优质、可信赖、高性能

专为网络设计的 VLP 模块

模块的核心采用全球最先进的 DRAM 技术，因此您的路由器、集线器、交换机或网桥可以更快、更小巧并更可信赖。事实上，VLP Mini-DIMM 专为网络而设计。美光是第一家提供 VLP Mini-DIMM 的内存制造商，而此产品现已成为行业标准产品。VLP Mini-DIMM 可以垂直安装，因此可以极大改善空气流通并减少热电消耗。节能的同时，您无需牺牲存储性能；我们的 VLP Mini-DIMM 是兼具创新型、可靠性和高带宽等特点的解决方案，并与现有插孔兼容。

VLP Mini-DIMM 料件目录和文档
 ATCA Compliant The standard for DDR3 VLP DIMMs is 18.75mm, which could cause conflicts for some ATCA systems.但是我们的 DDR3 VLP Mini-DIMM 将高度限制在 17.9 毫米，因此其仍然可以兼容 ATCA 设计中的插槽。

可带来完美数据保真性的 ECC
我们所有的 VLP Mini-DIMM 都拥有嵌入式 ECC，可靠保证高数据保真。注册版本还包括地址奇偶校验，这为对数据准确性有着严格要求的系统提供了更好的性能。地址奇偶校验受到一些控制器的支持并比 ECC 更进一步，允许系统设计者检验模块数据地址行的准确性。

行业领先的质量
我们开发制造高质量的网络模块，全程掌控模块生产过程。我们使用前沿的 DRAM 进行设计并与主板生产商和行业组织合作。我们认真测试元件、封装和模块。我们全程参与内存设计和生产，因此可以保证为您不断提供顶尖质量的 VLP Mini-DIMM。

特点 优势
Wide Density Range With many density choices in a small form factor, you can build powerful devices with a small footprint
Flexible Configuration Available as registered or unbuffered* in single- or dual-rank configurations (*UDIMMs in DDR3 only)
ECC ECC bits to support error handling and correction for increased data reliability
Optional PLL and Buffer Reduces the load on the memory controller, which ensures signal integrity and enables the system to accommodate the maximum number of modules
仿真模型 Our convenient thermal and electrical simulation models are available online for easy download

类型 安全 标题和描述 编号 更新日期 文件大小
Thermal Applications: 定义了测量和确保美光零件和模块不超过允许的最高温度的一般方法和标准 TN-00-08 2010/05 252.18 KB
Recommended Soldering Parameters: 定义了美光科技公司产品的推荐连接技术和参数。 TN-00-15 2007/03 69.09 KB
Uprating of Semiconductors for High-Temperature Applications: 描述了与提升温度有关的问题，以及在制造环境规范之外使用零件和/或系统的相关风险 TN-00-18 2010/05 428.33 KB
Understanding Signal Integrity: 描述了从新产品构思直至产品寿命结束的整个过程中，如何发挥内存设计、测试和验证工具的最大优势 TN-00-20 2009/12 1.52 MB
Memory Module Serial Presence-Detect: Describes how SPD is essential in helping to standardize the configuration, timing, and manufacturing information of memory modules TN-04-42 2009/12 505.83 KB
Comparing Module Parameters: Compares module parameters. TN-04-49 2003/03 52.71 KB
High-Speed DRAM Controller Design: Identifies and discusses five key areas of DRAM controller design TN-04-54 2008/04 1 MB
DRAM Module Form Factors: Compares the most common DRAM module form factors TN-04-55 2009/09 435.56 KB
Module Pinout Decoder: Provides sorted pin assignment tables and pin location figures for use in DDR2 DIMM signal identification, tracing, and troubleshooting TN-47-03 2004/12 215.46 KB
Module Part Numbering Systems: Part numbering guides for Micron DDR4, DDR3, DDR, DDR, and SDRAM modules. 2012/04 50.52 KB
PCN/EOL Systems: 介绍了美光产品的变更通知和寿命终结系统。 CSN-12 2012/04 79.21 KB
Wafer Packaging and Packaging Materials: 提供了有关装运美光产品时使用的各种材料的完整装运和回收信息。 CSN-20 2011/09 776.24 KB
Bare Die SiPs and MCMs: 描述了 Bare Die SiP 和 MCM 的设计考虑因素。 CSN-18 2009/04 151.06 KB
Shipping Quantities: 提供了料件数量表格。 CSN-04 2012/04 472.27 KB
Micron KGD Definitions: 描述了美光 KGD-C1 和 KGD-C2 DRAM 芯片的测试规格和参数 CSN-22 2009/07 65.52 KB
Proper Handling Procedures for Modules: 涵盖了如何正确操作模块的程序。 CSN-23 2007/12 1.02 MB
Micron Component and Module Packaging: 解释了美光的封装标签和程序。 CSN-16 2012/02 887.13 KB
ESD Precautions for Die/Wafer Handling and Assembly: 介绍了在工作场所中控制 ESD 的好处，包括提高产量和改善质量与可靠性，最终可以缩减制造成本。 CSN-24 2010/08 119.08 KB
Electronic Data Interchange: 描述了 EDI 传输的装置、协议和联系方式。 CSN-06 2005/09 53.5 KB
RMA Procedures for Packaged Product and Bare Die Devices: 概括介绍了标准的退货授权 (RMA) 程序，以及与 bare die RMA 的对比。 CSN-07 2010/10 82.64 KB
ISO System Management Standards: 描述了 ISO 系统管理标准。 CSN-08 2004/04 39.18 KB
Competitive DDR Memory Subsystems: DDR milestones and platform design 2009/12 2.64 MB
DDR System Design Considerations: DDR overview 2009/12 3.46 MB
The Future of Memory and Storage: 概述了主存和闪存的发展趋势 2009/12 1.54 MB
Design Guide for Two DDR3-1066 UDIMM Systems: Rev. B, Design guide to assist board designers implementing products using UDIMM systems TN-41-08 2010/01 1.1 MB
Moisture Absorption in Plastic Packages: Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 2010/02 87.26 KB
Accelerate Design Cycles with Simulation Models: 美光会提供必要的工具和指导，以在实际布局前对新设计进行检验。此技术要点讨论了软件模型支持、信号保真性优化和逻辑电路设计。 TN-00-09 2010/02 206.91 KB
Micron Wire-Bonding Techniques: 此技术要点提供了丝焊技术的指导，可用于美光产品的镍钯 (NiPd) 和铝制接合焊盘。 TN-00-22 2010/11 66.13 KB
Micron BGA Manufacturer's User Guide: 提供相关信息，帮助顾客轻松将最前沿的和传统的美光球栅阵列 (BGA) 封装整合到制造流程中。此指南旨在提供一系列高水平指导，并附有参考手册，其中介绍了封装相关和制造工艺流程的典型做法。 CSN-33 2011/07 353.32 KB
Proper Handling Procedures for Micron DIMMs:  2009/12 396.18 KB
Proper Installation Procedures for Micron DIMMs:  2009/12 419.89 KB
Proper Handling of Micron DIMMs - Japanese:  2009/12 453.96 KB
Proper Installation of Micron DIMMs - Japanese:  2009/12 394.2 KB
Proper Handling of Micron DIMMs - Simplified Chinese:  2009/12 482.47 KB
Proper Installation of Micron DIMMs - Simplified Chinese:  2009/12 592.58 KB
Proper Handling of Micron DIMMs - Spanish:  2009/12 461.82 KB
Proper Installation of Micron DIMMs - Spanish:  2009/12 546.81 KB
Proper Handling of Micron DIMMs - Traditional Chinese:  2009/12 539.92 KB
Proper Installation of Micron DIMMs - Traditional Chinese:  2009/12 758.93 KB
Product Marks/Product and Packaging Labels: 介绍了产品料件的标记，以及产品和封装的标签。 CSN-11 2012/04 724.89 KB
Bypass Capacitor Selection for High-Speed Designs: 描述了高速设计的旁路电容选择。 TN-00-06 2011/03 481.9 KB

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Is there a set of trace lengths and routing rules that are standard for use when designing a system that uses a specific module technology and form factor?
No. A robust memory subsystem design that includes the use of one or more memory modules must be simulated in order to determine the optimum trace lengths and terminations.However, our design guides such as TN-47-01 and TN-41-08 have some best practices and design examples based on some typical system assumptions.This information does not define the only way your system can be designed; it is a starting point and, moreover, an example of steps that can be taken to determine the best design for your system.
Can Vtt and Vref be supplied by the same supply in my system design?
With proper decoupling, this can be an acceptable design.However, Micron recommends separating all supplies.VREF tends to have more noise on it because it supplies signals that are regularly switching.A robust design typically would not connect these supplies due to the possibility of introducing this noise onto the VTT plane, which should be as stable as possible.Additionally, VREF requires much less current than VTT.

VLP Mini-DIMM

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